1. Technical Field
The present invention relates to a protection circuit and a semiconductor device, and in particular to a protection circuit for protecting an internal circuit from inflowing current due to electro-static discharge, and a semiconductor device provided with such a protection circuit.
2. Related Art
Sometimes violent electrical discharge occurs when a charged electrically conductive body (such as a person) makes contact or gets near to another conductive body (such as an electrical device). This phenomenon is referred to as electro-static discharge (ESD). In semiconductor devices, with the current trend towards higher levels of integration and even finer configuration elements of integrated circuits, preventing damage to internal circuits caused by inflow of external high voltage waveforms from ESD has become an issue.
As a technique for addressing this issue, a technique is known in which a protection circuit is provided to a semiconductor device. The protection circuit protects an internal circuit by responding to high voltage changes in either a power source line for applying a plus electrical potential used for driving to a semiconductor device, or in a ground line for applying a ground electrical potential to a semiconductor device, and eliminating the potential difference between the power source line and the ground line.
FIG. 7 schematically shows an example of a protection circuit layout in a semiconductor device. As shown in FIG. 7, a conventional semiconductor device 100 is configured including a protected circuit 102, equivalent to a semiconductor integrated circuit, and a protection circuit 104. The protected circuit 102 is equipped with a first terminal 102A, a second terminal 102B and a control terminal 102C. The first terminal 102A is connected to a power source line VDD, the second terminal 102B is connected to a ground (earth) line GND, and the control terminal 102C is connected through a resistor R to a pad P.
The semiconductor device 100 is equipped with a P-channel MOS transistor (referred to below as “PMOS transistor”) 106 and an N-channel MOS transistor (referred to below as “NMOS transistor”) 108. The drain terminals of each of the PMOS transistor 106 and the NMOS transistor 108 are connected to a connection point between the resistor R and the pad P. The source terminal, gate terminal and back gate terminal of the PMOS transistor 106 are connected to the power source line VDD, and the source terminal, gate terminal and back gate terminal of the NMOS transistor 108 are connected to the ground line GND.
The protection circuit 104 is equipped with a first terminal 104A and a second terminal 104B.
The first terminal 104A is connected to the power source line VDD and the second terminal 104B is connected to the ground line GND. In the semiconductor device 100 configured as described, when voltage of high voltage waveform occurring due to ESD (referred to below as “surge voltage”) is applied to either the power source line VDD or the ground line GND, the protected circuit 102 is protected due to the protection circuit 104 operating with the surge voltage as a trigger, so as to eliminate the potential difference between the power source line VDD and the ground line GND.
An example of a protection circuit 104 is schematically shown in FIG. 8. As shown in FIG. 8, the protection circuit 104 is configured including a single NMOS transistor 110, with the drain terminal of the NMOS transistor 110, serving as the first terminal 104A, connected to the power source line VDD, the source terminal the gate terminal, back gate terminal and source terminal of the NMOS transistor 110, serving as the second terminal 104B, connected to the ground line GND. The protection circuit 104 configured as described uses the breakdown characteristics of the NMOS transistor 110 to release charge caused by the surge voltage. Accordingly, for example, when a salicide structure transistor and high withstand voltage transistor, Silicon-On-Insulator (SOI) transistor, Silicon-On-Sapphire (SOS) transistor, or the like is employed as the NMOS transistor 110 in order to achieve an increase in speed, damage soon occurs when the NMOS transistor 110 is in breakdown operation.
There are known techniques, such as those described in Japanese Patent Application Laid-Open (JP-A) No. 2006-121007 and in JP-A No. 7-7406, for employing as the incorporated protection circuit 104 in order to prevent damage due to breakdown operation of the NMOS transistor 110.
FIG. 9 shows a schematic configuration of a protection circuit 104 applied in the techniques of JP-A No. 2006-121007 and JP-A No. 7-7406. As shown in FIG. 9, the protection circuit 104 is equipped with: a resistor 112 and a condenser 114, serving as a capacitive load, connected between the power source line VDD and the ground line GND; an inverter 116 having an input terminal 116A connected between the resistor 112 and the condenser 114; and an NMOS transistor 110 with gate terminal connected to the output terminal 116B of the inverter 116, drain terminal connected to the power source line VDD, and source terminal and back gate terminal connected respectively to the ground line GND.
The inverter 116 is a CMOS inverter configured by complementarily disposed PMOS transistor 118 and NMOS transistor 120. Namely, the inverter 116 has the gate terminal of the PMOS transistor 118 and the gate terminal of the NMOS transistor 120 connected together, this connection point configuring the input terminal 116A, the drain terminal of the PMOS transistor 118 and the drain terminal of the NMOS transistor 120 connected together, this connection point configuring the output terminal 116B, the source terminal and the back gate terminal of the PMOS transistor 118 connected to the power source line VDD, and the source terminal and the back gate terminal of the NMOS transistor 120 connected to the ground line GND.
The protection circuit 104 configured as described can prevent damage due to breakdown of the NMOS transistor 110 by employing the frequency characteristics of an RC circuit configured by the resistor 112 and the condenser 114.